As the feature size of a CMOS device gradually shrinks, it enters into a deep submicron and a nanometer regime. However, its parasitic capacitance, especially a fringing parasitic capacitance between a gate and a source/drain (FIG. 1), may not shrink correspondingly, which accounts for an increasing proportion in the total capacitance, resulting in a severe influence on the transient response of the device.
On the other hand, short channel effect (SCE), which manifest itself as the threshold voltage roll-off, increased subthreshold slope and subthreshold leakage current etc., has become an important issue, when the device enters into a deep submicron regime In order to mitigate SCE, a conventional planar transistor can be reformed by a novel structure. Due to a surrounding gate structure and a channel diameter in nanometer regime, a surrounding gate silicon nanowire transistor has a very excellent capability in controlling the short channel effect, which is a promising novel device structure to replace the conventional planar transistor in the case of a very short channel. Since the channel diameter of the surrounding gate nanowire transistor is in a nanometer regime, its intrinsic capacitance is very small, however, the fringing capacitance from the gate to the source/drain is comparatively large (FIG. 2). As a result, the parasitic capacitance has more significant influence on the transient response compared with that of the planar transistor.
The fringing capacitance between the gate and the source/drain region can be reduced by using material with a low dielectric constant as spacers. Since the air has a very low dielectric constant, it can be perceived that the surrounding gate nanowire transistor using air as sidewalls will has smaller parasitic capacitance. FIG. 3 is a schematic diagram of a surrounding gate nanowire transistor using conventional SiO2 spacers and air spacers. FIGS. 4 and 5 are the cross section views of the device taken along the line AA′ and line BB′. FIGS. 6(a) and 6(b) are the schematic diagrams of the surrounding gate nanowire transistor with a channel length of 20 nm, a nanowire diameter of 10 nm, and a spacer thickness of 10 nm using conventional SiO2 spacers and air spacers, respectively. FIG. 6(c) is the comparison of their gate capacitances, and it is shown that the parasitic capacitance is largely reduced by using air spacers.
So far, the experiment research on the surrounding gate nanowire transistor is mainly focused on the process integration, electrical characterization, and device optimization to reduce parasitic resistance. However, there is no report on the optimization for parasitic capacitance in this device. Furthermore, due to a special three dimensional structure of the nanowire, how to form air sidewalls needs a special design of process flow. And this has not been reported by now.